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this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this procuts. no rights under any patent accompany the sales o f the product. 1/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology features general description block diagram ? ieee802.3 and ieee802.3u compliant. ? provide 4 rmii and 1 mii/rmii ports. ? programmable 1k/8k mac addresses filtering. ? store and forward switching function and bad packet filtering function. ? optional back_pressure/802.3x flow control/ flooding control/broadcast control. ? optional eeprom interface for advanced switch configurations. ? 1mb/2mb sgram/sdram flexible memory interface. ? port vlan/trunking. ? link/rx activity, packet buffer utilization led display. ? 50mhz for non-blocking for 5 ports switch oper- ation ? build in internal/external memory test function. ? 128 pin pqfp package, 3.3v operation volt- age. 5 port 10m/100m ethernet switch the mtd505 complies fully with the ieee802.3, 802.3u and 802.3x specifications and is a non-blocking 5 port 10m/100m ethernet switch device. support 4 rmii and 1 mii/rmii ports for 10m/100m operation. 1mbyte/2mbytes memory interface provides maximum 1365 packet buffers for ethernet packet buffering. up to 8192 address entrys are provided by the mtd505, and the mtd505 use full ethernet address compare algo- rithm to minimize hashing collision events. the mtd505 provides eeprom interface to config port trunking, port vlan, static entry, 802.3x flow control threshold, flooding port, broadcast control threshold. each mtd505 port support 10/100m auto-negotiation by mdc/mdio interface for connecting external phy devices. the mtd505 also provides 10 pins for link/rx activity, packet buffer utilization led dis- play function. sdram/ port switch logic rmii/mii4 mac4 dma4 rmii3 mac3 dma3 rmii0 mac0 dma0 rmii1 mac1 dma1 rmii2 mac2 dma2 memory arbiter memory controller sgram interface
this datasheet contains new product information. myson technology reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this procuts. no rights under any patent accompany the sales o f the product 2/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology system diagram mtd505 quad physceiver single physceiver rmii0-3 mii4 quad transformer single transformer rj45 rj45 eeprom leds sgram (256k32x2) sgram (512k32x1) sgram (256k32x1) (**option) (**programmable) mii management
3/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology 1.0 pin connection 1 0 2 1 0 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 l e d d a t a 5 l e d d a t a 6 l e d d a t a 7 v c c o g n d o l e d c l k 2 l e d c l k 1 d q 0 d q 1 d q 2 d q 3 d q 4 d q 5 d q 6 d q 7 d q 1 6 d q 1 7 d q 1 8 d q 1 9 d q 2 0 v c c o g n d o d q 2 1 d q 2 2 d q 2 3 w e b c a s b r a s b c s 0 b b a v c c i g n d i c s 1 b a d 0 a d 1 a d 2 a d 3 a d 4 leddata4 leddata3 leddata2 leddata1 leddata0 gndi clk25m vcci sdc sdio eeclk eedata resetb refclk mdio mdc crsdv0 txd0_1 txd0_0 txen0 rxd0_0 rxd0_1 crsdv1 txd1_1 txd1_0 txen1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 r x d 1 _ 0 r x d 1 _ 1 c r s d v 2 t x d 2 _ 1 t x d 2 _ 0 t x e n 2 g n d o v c c o r x d 2 _ 0 r x d 2 _ 1 c r s d v 3 t x d 3 _ 1 t x d 3 _ 0 t x e n 3 r x d 3 _ 0 r x d 3 _ 1 c r s d v 4 c o l 4 t x d 4 _ 3 t x d 4 _ 2 t x d 4 _ 1 t x d 4 _ 0 t x e n 4 t x c 4 r x c 4 r x d v 4 g n d i v c c i r x d 4 _ 0 r x d 4 _ 1 r x d 4 _ 2 r x d 4 _ 3 g n d i v c c i g n d i s y s c l k v c c i d q 3 1 mtd505 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 vcco gndo ad5 ad6 ad7 ad8 vcci memclk gndi dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq24 dq25 dq26 vcco gndo dq27 dq28 dq29 dq30
4/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology 2.0 pin descriptions rmii/mii port interface pins name pin number i/o descriptions crsdv0 119 i port0 rmii receive interface signal, crsdv0 is asserted high when port0 media is non_idle. rxd0_0 rxd0_1 123 124 i i port0 rmii receive data bit_0. port0 rmii receive data bit_1. txen0 122 o port0 rmii transmit enable signal. txd0_0 txd0_1 121 120 o o port0 rmii transmit data bit_0. port0 rmii transmit data bit_1. crsdv1 125 i port1 rmii receive interface signal, crsdv1 is asserted high when port1 media is non_idle. rxd1_0 rxd1_1 01 02 i i port1 rmii receive data bit_0. port1 rmii receive data bit_1. txen1 128 o port1 rmii transmit enable signal. txd1_0 txd1_1 127 126 o o port1 rmii transmit data bit_0. port1 rmii transmit data bit_1. crsdv2 03 i port2 rmii receive interface signal, crsdv2 is asserted high when port2 media is non_idle. rxd2_0 rxd2_1 09 10 i i port2 rmii receive data bit_0. port2 rmii receive data bit_1. txen2 06 o port2 rmii transmit enable signal. txd2_0 txd2_1 05 04 o o port2 rmii transmit data bit_0. port2 rmii transmit data bit_1. crsdv3 11 i port3 rmii receive interface signal, crsdv0 is asserted high when port3 media is non_idle. rxd3_0 rxd3_1 15 16 i i port3 rmii receive data bit_0. port3 rmii receive data bit_1. txen3 14 o port3 rmii transmit enable signal. txd3_0 txd3_1 13 12 o o port3 rmii transmit data bit_0. port3 rmii transmit data bit_1. crsdv4 17 i port4 rmii/mii receive interface signal, crsdv4 is asserted high when port4 media is non_idle. rxdv4 26 i port4 mii receive data valid. in rmii mode, this pin don?t use. rxclk4 25 i port4 mii receive clock signal. in rmii mode, this pin is not used. rxd4_3 rxd4_2 rxd4_0 rxd4_1 32 31 29 30 i i i i port4 mii receive data bit_3. in rmii mode, this pin don?t use. port4 mii receive data bit_2. in rmii mode, this pin don?t use. port4 rmii/mii receive data bit_0. port4 rmii/mii receive data bit_1. txen4 23 o port4 rmii transmit enable signal. txclk4 24 i port4 rmii transmit clock signal. in rmii mode, this pin is not used.
5/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology note: sgram/sdram access time: 10 ns (max) txd4_3 txd4_2 txd4_0 txd4_1 19 20 22 21 o o o o port4 mii transmit data bit_3. in rmii mode, this pin don?t use. port4 mii transmit data bit_2. in rmii mode, this pin don?t use. port4 rmii/mii transmit data bit_0. port4 rmii/mii transmit data bit_1. col4 18 i port4 mii collision input. in rmii mode, this pin don?t use. clk25m 109 o port4 mii 25mhz clock output. sgram/sdram interface pins name pin number i/o descriptions ad[8:0] 59,60,61,62, 65,66,67,68, 69 o memory row/column address bus outputs ad[7:0] are row/column address [7:0]. ad[8] : this pin should connect to sgram/sdram msb address bit. dq[31:0] 38~42,45~55 ,78~80, 83~95 i/o memory data bus rasb 75 o sgram/sdram row address select casb 76 o sgram/sdram column address select web 77 o sgram/sdram write enable ba 73 o sgram/sdram bank select cs0b 74 o memory chip select 0 cs1b 70 o memory chip select 1 memclk 57 o memory clock output. led interface pins name pin number i/o descriptions leddata [7:0] 100,101,102, 103,104,105, 106,107 i/o led data output. these led pins report port0~7 link/rx activity status using ledclk1 strobe , and report packet buffer utilization status using ledclk2 strobe. leddata [0] [1] [2] [3] [4] [5] [6] [7] ledclk1 lr0 lr1 lr2 lr3 lr4 --- --- --- ledclk2 uti0 uti1 uti2 uti3 uti4 --- bfull mfail note: lrn: means per port?s link_rxact status. uti0: 5%, uti1: 10%, uti2: 20%, uti3: 35%, uti4: 50 above . bfull: buffer almost full alarm signal. mfail: external memory poer on test failure. rmii/mii port interface pins name pin number i/o descriptions
6/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology ledclk1 96 i/o led strobe 1 ledclk2 97 i/o led strobe 2 miscellaneous pins name pin number i/o descriptions resetb 115 i system reset input, low active. sysclk 36 i switch core system clock input, using the same clock source with ref- clk. refclk 116 i rmii reference clock input, using 50mhz. mdc 118 i/o mii management clock inout mdio 117 i/o mii management data inout sdc 111 i/o mii register clock inout sdio 112 i/o mii register data inout eedata 114 i/o eeprom data input eeclk 113 i/o eeprom clock output vcc 08,28,34,37, 44,58,64,72, 82,99,110 pwr power pins gnd 02,27,33,35, 43,56,63,71, 81,98,108 gnd ground pins led interface pins name pin number i/o descriptions
7/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology jummper configuration after power on reset name pin number i/o descriptions leddata[0] leddata[1] leddata[2] leddata[3] leddata[4] leddata[5] leddata[6] leddata[7] i/o during power on reset duration, these pins are jumper setting pins (pull_hgih = 1, pull_low = 0). leddata[0] : select sgram/sdram interface , ?1? means 256k32 x 1 or 512k32 x 1 is selected. ?0? means 256k32 x 2 is selected, default is ?1?. leddata[1] : config packet buffer size, ?1? means 2 m bytes buffer size is selected. ?0? means 1 m byte buffer size is selected, default is ?0? leddata[2] : enable memory test function, ?1? means enable. ?0? means disable, default is ?1?. leddata[3] : enable aging function, ?1? means enable. ?0? means disable, default is ?1?. leddata[4] : enable mii polling(mdc/mdio), ?1? means enable. ?0? means disable, default is ?1?. leddata[5] : enable broadcast storm control, ?1? means enable. ?0? means disable, default is ?1?. leddata[6] : enable backpressure function (in half mode), ?1? means enable. ?0? means disable, default is ?1?. leddata[7] : enable 802.3x flow control function (in full mode) , ?1? means enable. ?0? means disable, default is ?1?. ledclk1 i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). ledclk1 : select 1k or 8k address entry table, ?1? means 8k addres entry is selected. ?0? means 1k address entry is selected, default is ?1?. ledclk2 i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). ledclk2 : enable eeprom interface. ?1? means enable. ?0? means disable, default is ?1?.
8/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology eedata i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). eedata : enable eeprom auto_load configuration function while eeprom interface is enabled, ?1? means enable. ?0? means disable, default is ?1?. txen[2:0] i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). txen[2:0] : uplink port (flooding port) 0 ~7 selection; default is ?000?. txen[3] i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). txen[3] : enable flooding control, ?1? means enable. ?0? means disable, default is ?0?. txen[4] i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). txen[4] : enable vlan tag 1522 bytes receiving, ?1? means enable. ?0? means disable, default is ?0?. sdc i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). sdc : port4 mii/rmii interface selection, ?1? means port4 mii interface is selected. ?0? means port4 rmii interface is selected, default is ?0?. eeclk i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). eeclk : scan mode enable for debugging purpose, ?1? means scan mode enable. ?0? means scan mode disable, default is ?0?. mdc i/o during power on reset duration, this pin is a jumper setting pin (pull_hgh =1, pull_low = 0). mdc : fast mode enable for testing purpose, ?1? means fast mode enable. ?0? means fast mode disable, default is ?0?. jummper configuration after power on reset name pin number i/o descriptions
9/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology 3.0 functional descriptions the mtd505 is an 5 ports 10/100 mbps fast ethernet switch controller. it is a low cost solution for eight ports fast ethernet soho switch design. no cpu interface is required; after power on reset, mtd505 provide an auto load configuration setting function through a 2 wire serial eeprom interface to acess external eeprom device, and mtd505 can easily be configured to support port_trunking, port_ vlan, static entry, 802.3x flow control threshold setting , flooding port assignment ...etc functions. the follow- ing descriptions are mtd505?s major functional blocks overview. 3.1 packet store and forwarding the mtd505 use simple store and forward algorithm as packet switching method. input packet from ports will be stored to external memory first, while packet is good for forward (crc chech ok, 64bytes < length < 1518bytes, not local packets, in the same vlan group ) , if this packet?s da hits, than forward this packet to the destination port, otherwise this packet will be broadcasted. 3.2 learning and routing the mtd505 supports 1k or 8k mac entries for switching. dynamic address learning is performed by each good unicast packet is completely received. the static address learning is achieved by eeprom configuration. on the other hand, the routing process is performed whenever the packet?s da is cap- tured. if the da can not get a hit result, the packet is going to switch broadcast or forward to the dedi- cated port according to the flooding control selction. 3.3 aging only the dynamic address entries are scheduled in the aging machine. if one station does not transmit any packet for a period of time, the belonging mac address will be kicked out from the address table. the aging out time can be program through the eeprom auto load configuration. (default value is 300 seconds) 3.4 buffer queue management the buffer queue manager is implemented to manage the external shared memory (use sdram/ sgram) for packet buffering. the main function of the buffer queue manager is to maintain the linked list consists of buffer ids, which is used to show the corresponding memory address for each incoming packet. in addition, the buffer queue manager monitors the rested free spaces status of the external memory, if the packet storage achieve the predefined threshold value, the buffer queue manager will raise the alarm signal which is used to enable the flow control mechanism for avoiding transmission id queue overflow happening. mtd505 provide 802.3x flow control in full duplex mode and back pressure control in half duplex mode. 3.5 full duplex 802.3x flow control in full duplex mode, mtd505 supports the standard flow control defined in ieee802.3x standard. it enables the stopping of remote node transmissions via a pause frame information interactoin. when the ?802.3x flow control enable? bit is set during power on reset (leddata[7] pin is external pull_high), it enables mtd505 supporting 802.3x flow control function in full_duplex mode; when output port buffer queue?s on_using value reach the initialization setting threshold value (recommended xon_th = 74?h when using 2mbytes external memory; xon_th = 2e?h when using 1mbytes external memory), mtd505 will send out a pause packet with pause time equal to fff to stop the remote node transmis- sion; when the output port buffer queue?s on_using value reduce to the initialization threshold value(recommended xoff_th = 30?h when using 2mbytes external memory; xoff_th=18?h when using 1mbytes external memory), mtd505 will also send a pause packet with pause time equal to zero to inform the remote node to retransmit packet.
10/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology 3.6 half duplex back pressure control in half duplex mode, mtd505 provide a back pressure control mechanism to avoid dropping packets during network conjection situation. when the ?back pressure control enable? bit is set during power on reset (leddata[6] pin is external pull_high), it enables mtd505 supporting back pressure function in half_duplex mode; when output port buffer queue?s on_using value reach the initialization setting threshold value (same with the xon_th value), mtd505 will send a jam pattern in the input port when it senses an incoming packet , thus force a collision to inform the remote node transmission back off and will effectively avoid dropping packets. if the ?back pressure control enable? bit is not set, and there is no free buffer queue available for the incoming packets, the incoming packets will be dropped. 3.7 mii polling the mtd505 supports phy management through the serial mdio/mdc interface. after power on reset, the mtd505 write related abilities to the advertisement register 4 of connected phy devices and restart the auto_negotiation prcedure via mdio/mdc interface using the predefined phy addresses increasingly from ?01000?b to ?01100?b. the mtd505 will periodically and continuously poll and update the link status and link partner?s ability which include speed, duplex mode, and 802.3x flow control capable status of the connected phy devices through mdio/mdc serial interface. 3.8 mac and dma engine the mtd505?s mac performs all the functions in ieee802.3 protocol, such as frame formatting, frame stripping, crc checking, bad packet dropping, defering to line traffic, and collision handling. the mac rx_engine checks incoming packets and drops the bad packet which include crc error, alignment error, short packet (less than 64 bytes), and long packet(more than 1518 bytes or 1522 bytes when the ?vlan tag 1522 bytes receive enable? bit is set during power on reset). before transmission, the mac tx_engine will constantly monitor the line traffic using derfering precedure. only if it has been idle for a 96 bits time (a minimum interpacket gap time, ipg time), actual transmmission can be started. for the half duplex mode, mac engine will detect collision; if a collision is detected, the mac tx_engine will transmit a jam pattern and then delay the re_transmission for a random time period determined by the back_off algorithm (mtd505 implements the truncated exponential back_off algorithm defined in ieee 802.3 standard). for the full duplex mode, collision signal is ignored. the mtd505?s dma engine performs the packets non_blocking transportation between mac engine and external memory according to a high speed switching procedure. the switching procedure is com- pleted by address learning/routing process and buffer queue management operation. 3.9 eeprom interface mtd505 provide an auto load configuration setting function through a 2 wire serial eeprom interface to acess external eeprom device(24c02) after power on reset . mtd505 can easily be configured to support port_trunking, port_ vlan, static entry, 802.3x flow control threshold setting , flooding port assignment ...etc functions. the following table is the eeprom contents mapping: name eeprom address eeprom content description recommended value under basic operation eob 00 last eeprom content address value 8?h13 agelow 01 aging time bit [7:0] 8?h2c agehigh 02 aging time bit [15:8] 8?h01 vlan0 03 port0 vlan register 8?hfe vlan1 04 port1 vlan register 8?hfd vlan2 05 port2 vlan register 8?hfb vlan3 06 port3 vlan register 8?hf7 vlan4 07 port4 vlan register 8?hef
11/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology 3.10 port based vlan the mtd505 supports vlan configuration by port based methodology. one port select the certain ports to form its vlan group by configuring the vlan register. the packet (including broadcast packet) is not forwarding to the destination port whose vlan group is different from the source port. reserved 08 reserved 8?hdf reserved 09 reserved 8?hbf reserved 0a reserved 8?h7f uplink10 0b bit[7:4] --- the flooding port_no of port1 bit[3:0] --- the flooding port_no of port0 *ex1: bit[7:4] = ?0011?b, means that if the incomin packet of port1 got the ?un_routed? result, then this incoming packet will be flooded to port3. *ex2: bit[3:0] = ?0111?b, means that if the incomin packet of port0 got the ?un_routed? result, then this incoming packet will be flooded to port7. (note: set value ?4?hf?, means flooding to all the other ports; set value ?4?h8?~?4?he? is forbidden) 8?h0f uplink32 0c bit[7:4] --- the flooding port_no of port3 bit[3:0] --- the flooding port_no of port2 (note: set value ?4?hf?, means flooding to all the other ports; set value ?4?h8?~?4?he? is forbidden) 8?h00 uplink54 0d bit[7:4] --- reserved bit[3:0] --- the flooding port_no of port4 (note: value setting ?f?, means flooding to all the other ports; value setting ?8? ~ ?e? is forbidden) 8?h00 reserved 0e reserved 8?h00 broadcast th 0f broadcast threshold 8?hff xon th 10 xon threshold 8?h74 xoff th 11 xoff threshold 8?h30 disport 12 disable port 8?h00 system control 13 system control byte : bit[0] --- enhanced back pressure enable, bit[7:1] --- reserved. 8?h00 reserved 14 ~1f none staticsa1 20 ~26 address 26 bit[2:0] --- means port id address 25 bit[7:0] ~ address 20 bit[7:0] --- means static sa[47:0] staticsa2 27 ~ 2d address 2d bit[2:0] --- means port id address 2c bit[7:0] ~ address 27 bit[7:0] --- means static sa[47:0] name eeprom address eeprom content description recommended value under basic operation
12/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology 3.11 port trunking the port trunking function can also be implemented by vlan registers. one trunk port isolates the packet transmitting and receiving from the other trunk ports, which performs a logical trunk topology. the non-trunk port should choose only one trunk port for transmitting, which can achieve the load bal- ancing and maintain the packet sequences. 3.12 memory interface two kinds of external memory interface can be selected by user -- 1m byte memory (256k32 x 1) and 2 m bytes (256k32 x 2 or 512k32 x 1). maximum 2m byte external memory can be used for packet buff- ering. ?-10 ? speed grade of sgram/sdram device is recommanded. the following table is the sgram application pin connection : 3.13 internal mii registers acess and control the mtd505 support 2 serial pins (sdio/sdc) for internal registers acess and control; the detailed registers informations are presented in section4.0 (internal mii registers). 3.14 led display the mtd505 use 10 pins to output 2 kinds of led display -- leddata[7:0], ledclk1, ledclk2. using ledclk1 rising edge, leddata[7:0] report port7~0 link/receive activity led status. using ledclk2 rising edge, leddata[4:0] report packet buffer utilization rating, and leddata[7] report external memory test result(after power reset, mtd505 will test external sdram automatically), led- data[6] report the buffer almost full alarm signal . 4.0 internal mii registers the mtd505 implements 10 mii global registers and 4 per port registers, define as following tables: memory type memory chip no a[8] cs0b cs1b 256k32 x 1 a8 cs0b nc 256k32 x 2 a8 cs0b cs1b 512k32 x 1 a9 cs0b a8 table 1. mii registers global registers reg no bits name r/w descriptions default 0 ctlreg0 r/w control register 0 8-0 bit[0] = 1 --> switch to port 0 registers bit[1] = 1 --> switch to port 1 registers bit[2] = 1 --> switch to port 2 registers bit[3] = 1 --> switch to port 3 registers bit[4] = 1 --> switch to port 4 registers bit[5] = reserved bit[6] = reserved bit[7] = reserved bit[8] = 1 --> switch to global registers 9?h100 12-9 scan mode select 3-0 15-13 scan port select 1 ctlreg1 r/w control register 1 16?h3084
13/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology 7-0 xon xon threshold. 15-8 xoff xoff threshold. while eeprom is enabled, this register?s content will be updated by eeprom read xon/xoff threshold data automatically. after eeprom read is done, this register can be read/write by management cmd. default is 16?h3084(2m memory) or 16?h1838(1m mem- ory) 2 ctlreg2 r/w control register 2 16?d300 15-0 aging bit[15:0] can specify aging time. while eeprom is enabled, this register?s content will be updated by eeprom read aging timer data auto- matically. after eeprom read is done, this register can be read/write by management cmd. 3 ctlreg3 r/w control register 3 16?h000f 15-0 uplink reg0 bit[15:12] specify port 3?s uplink port id. bit[11:8] specify port 2?s uplink port id. bit[7:4] specify port 1?s uplink port id. bit[3:0] specify port 0?s uplink port id. default is 16?h000f. p.s this register?s write sequence is jumper setting ==> eeprom content ==> mii management command. 4 ctlreg4 r/w control register 4 16?h0 15-0 uplink reg1 bit[15:12] :reserved bit[11:8] : reserved bit[7:4] : reserved bit[3:0] specify port 4?s uplink port id. default is 16?h0. p.s this register?s write sequence is jumper setting ==> eeprom content ==> mii management command. 5 ctlreg5 r/w control register 5 16?hff 7-0 bit[7:0] specify broadcast threshold. 8 bit[8] enable enhance backpressure. 15-9 reserved. p.s this register can be writed by eeprom content or mii management command too. 6 stsreg0 ro/ rc status register 0 7-0 bit[4:0] outputs port4-0 rxdma fifofull, bit[7:5] : reserved. table 1. mii registers global registers reg no bits name r/w descriptions default
14/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology 15-8 bit[12:8] outputs port4-0 txdma tpur(fifoempty), bit[15:13] : reserved. 7 stsreg1 ro status register 1 0 bufbistdone. 1 bufbisterr. 2 bufinitdone. 3 addrtblbistdone. 4 addrtblbisterr. 5 lthtblbistdone. 6 lthtblbisterr. 7 membistdone. 8 membisterr. 9 eedone. 10 freecntis0. 15-11 reserved. 8 ctlreg7 r/w control register 7 7-0 bit[4:0] output mii polling port4-0 flow control informa- tion, bit[7:5] : reserved 15-8 bit[12:8] output mii polling port4-0 link information, bit[15:13] : reserved. "1" means flow control enable or link good. 9 ctlreg8 r/w control register 8 7-0 bit[4:0] output mii polling port4-0 speed information, bit[7:5] : reserved. 15-8 bit[12:8] output mii polling port4-0 full information, bit[15:13] :reserved. "1" means 100m or full duplex. port registers 1 stsreg1 ro status register 1 10-0 bit[10:0] output port tx queue head value. 15-11 reserved. 2 stsreg2 ro status register 2 10-0 bit[10:0] output port tx queue tail value. 15-11 reserved. 3 stsreg3 ro status register 3 10-0 bit[10:0] output port tx queue count value. 15-11 reserved. 4 ctlreg1 r/w control register 1 7-0 bit[7:0] select port vlan group. 15-8 reserved. table 1. mii registers global registers reg no bits name r/w descriptions default
15/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology "r/w" means read/writable. 5.0 electrical characteristics 5.1 absolute maximum ratings 5.2 recommended operating conditions 5.3 dc electrical characteristics (under recommended operating conditions and vcc = 3.0 ~ 3.6v, tj = 0 to +115 o c) symbol parameter rating unit v cc power supply voltage -0.3 to 3.6 v v in input voltage -0.3 to vcc+0.3 v v out output voltage -0.3 to vcc+0.3 v t stg storage temperature -55 to 150 o c symbol parameter min. typ. max. unit v cc power supply 3.0 3.3 3.6 v v in input voltage 0 - vcc v t j commercial junction operating temperature 0 25 115 o c industrial junction operating temperature -40 25 125 o c symbol parameter conditions min. typ. max. unit i il input leakage current no pull-up or down -1 1 ua i oz tri-state leakage current -1 1 ua c in input capacitance 2.8 pf c out output capacitance 2.7 4.9 pf c bid3 bi-direction buffer capacitance 2.7 4.9 pf v il input low voltage cmos 0.3*vcc v v ih input high voltage cmos 0.7*vcc v v oh output high voltage i ol =2,4,8,12,16,24ma 0.4 v v ol output low voltage i oh =2,4,8,12,16,24ma 2.4 v r i input pull-up/down resistance v il =0v or v ih =v cc 75 kohm
16/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology 5.4 electrical characteristics symbol parameter min. typ. max. unit note t1 rmii input setup time 1 ns t2 rmii input hold time 1 ns t3 rmii output setup time 3 ns t4 rmii output hold time 5 ns symbol parameter min. typ. max. unit note t5 mii input setup time 10 ns t6 mii input hold time 10 ns t7 mii output setup time 3 ns t8 mii output hold time 5 ns figure 1. rmii timing refclk crsdv txen txd[1:0] rxd[1:0] t1 t2 t3 t4 valid valid figure 2. mii timing rxclk0 crs0/rxdv0 txen0 txd0[3:0] rxd0[3:0] t5 t6 t7 t8 valid valid txclk0
17/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology symbol parameter min. typ. max. unit note t5 memory clock cycle 12 ns t6 memory command/address/data setup time 6 ns t7 memory command/address/data hold time 2 ns t8 row active to burst write 2 clk figure 3. memory write timing rasb ad[8:0] t6 t5 valid casb t7 valid dq[31:0] valid t6 t7 t8 web memclk t6 t7 t6 t7 figure 4. memory read timing rasb ad[8:0] t6 t5 valid casb t7 valid dq[31:0] valid t6 t7 t8 web memclk t6 t7 t9 t10
18/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology symbol parameter min. typ. max. unit note t10 memory read data setup time 2 ns t11 memory ead data hold time 2 ns symbol parameter min. typ. max. unit note t11 eeprom clock cycle 10 us t12 eedata input setup time 1 ns t13 eedata input hold time 1 ns symbol parameter min. typ. max. unit note t14 led display strobe period 20 us t15 ledclk setup time 5 us t16 ledclk hold time 5 us figure 5. eeprom timing eeclk t11 t13 eedata valid t12 figure 6. led interface ledclk2 t16 leddata valid t15 ledclk1 valid valid t14
19/19 mtd505 revision 1.2 14/04/2000 mtd505 (preliminary) myson technology 6.0 128 pin pqfp package data 103 128 1 38 39 64 65 102 seating plane see detail a a a 1 a 2 e b d 1 d e 1 e l l1 z detail a note: 1.dimension d1 & e1 do not include mold protrusion. but mold mismatch is included. allowable protrusion is .25mm/.010? per side. 2.dimension b does not include dambar protrusion. allowable dambar protru- sion .08mm/.003?. total in excess of the b dimemsion at maximum material condition. dambar cannot be located on the lower radius or the foot. 3.controlling dimension : millimeter. symbol dimension in inch dimension in mm min norm max min norm max a - - 0.134 - - 3.40 a1 0.010 - - 0.25 - - a2 0.107 0.112 0.117 2.73 2.85 2.97 b 0.007 0.009 0.011 0.17 0.22 0.27 c 0.004 - 0.008 0.09 - 0.20 d 0.906 0.913 0.921 23.00 23.20 23.40 d 1 0.783 0.787 0.791 19.90 20.00 20.10 e 0.669 0.677 0.685 17.00 17.20 17.40 e 1 0.547 0.551 0.555 13.90 14.00 14.10 e 0.020 bsc 0.50 bsc l 0.029 0.035 0.041 0.73 0.88 1.03 l1 0.063 bsc 1.60 bsc y - - 0.004 - - 0.10 z 0 o - 7 o 0 o - 7 o y see detail b detail b c b with plating base metal gage plane

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